This invention relates to an analog buffer circuit, in particular, to an analog buffer circuit having a linear input-output voltage characteristic and a high input impedance.
A conventional analog buffer circuit has a complicated circuitry to have a linear input-output voltage characteristic for a predetermined range of input voltage. A simpler analog buffer circuit is configured using a differential circuit and a mirror circuit. Such an analog buffer circuit is disclosed in Unexamined Japanese Patent Publication No. 7-191393.
Recently, there is a demand to miniaturize each circuit included in a large scale integrated circuit with increase of demand for higher degree of integration with regard to the large scale integrated circuit. However, it is difficult to meet the demand because of the complicated circuitry with regard to the analog buffer.